Global Interconnect Optimization
نویسندگان
چکیده
We propose a new comprehensive solution to global interconnect optimization. Traditional buffering algorithms mostly insert repeaters on net-by-net basis based slacks and possibly guided by wires. show how integrate routing congestion, placement timing constraints, power consumption, additional constraints into single resource sharing formulation. The core of our algorithm is buffered subroutine. Given net Lagrangean prices for routing, timing, placement, power, it computes Steiner tree. framework provides special multiplicative price update fast convergence. Our enough practical instances. demonstrate experimentally 7nm microprocessor units that significantly improves while reducing netlength consumption in an industrial design flow. implementation scales well under parallelization with up 128 threads.
منابع مشابه
Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization
This paper presents an interconnect-driven floorplanning (IDFP) flow and algorithm integrated with multi-layer global wiring planning (GWP). It considers a number of interconnect performance optimizations during floorplanning, including interconnect topology optimization, layer assignment, buffer insertion, wire sizing and spacing. It also includes fast routability estimation and performance-dr...
متن کاملEffects of Temperature in Deep-Submicron Global Interconnect Optimization
The resistance of on-chip interconnects and the current drive of transistors is strongly temperature dependent. As a result, the interconnect performance is affected by the temperature in a sizeable proportion. In this paper we evaluate thermal effects in global RLC interconnects and quantify their impact in a standard optimization procedure in which repeaters are used. By evaluating the differ...
متن کاملFast interconnect optimization
Fast Interconnect Optimization. (December 2005) Zhuo Li, B.E., Xi’an JiaoTong University; M.S., Xi’an JiaoTong University Chair of Advisory Committee: Dr. Weiping Shi As the continuous trend of Very Large Scale Integration (VLSI) circuits technology scaling and frequency increases, delay optimization techniques for interconnect are increasingly important for achieving timing closure of high per...
متن کاملInterconnect Design Using Convex Optimization
Two wire sizing formulations for optimizing interconnect are presented. The rst minimizes the delay under wire width constraints, while the second minimizes the wiring area under delay and width constraints. A convex programming formulation is proposed, and an e cient algorithm is used to perform the optimization. Experimental results show that the rst formulation, which has been the prevalent ...
متن کاملInductive interconnect width optimization for low power
The width of an interconnect line a ects the total power consumed by a circuit A tradeo exists however between the dynamic power and the short circuit power in determin ing the width of inductive interconnect The optimum line width that minimizes the total transient power dissipation is determined in this paper A closed form solution for the op timum width with an error of less than is presente...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: ACM Transactions on Design Automation of Electronic Systems
سال: 2023
ISSN: ['1084-4309', '1557-7309']
DOI: https://doi.org/10.1145/3587044